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| MC74VHCT50A Noninverting Buffer / CMOS Logic Level Shifter with LSTTL-Compatible Inputs The MC74VHCT50A is a hex noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffered output which provides high noise immunity and stable output. The device input is compatible with TTL-type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic-level translator from 3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high-voltage power supply. The MC74VHCT50A input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHCT50A to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. http://onsemi.com 14-LEAD SOIC D SUFFIX CASE 751A 14-LEAD TSSOP DT SUFFIX CASE 948G 14-LEAD SOIC EIAJ M SUFFIX CASE 965 PIN CONNECTION AND MARKING DIAGRAM (Top View) VCC 14 A6 13 Y6 12 A5 11 Y5 10 A4 9 Y4 8 * * * * * High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 2 A (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V CMOS-Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load Power Down Protection Provided on Inputs and Outputs 1 A1 2 Y1 3 A2 4 Y2 5 A3 6 Y3 7 GND For detailed package marking information, see the Marking Diagram section on page 4 of this data sheet. LOGIC DIAGRAM A1 A2 A3 1 3 5 2 4 6 Y1 A1 Y2 Y3 Y=A Y4 Y5 A6 A6 13 12 Y6 A2 A3 A4 A5 LOGIC SYMBOL ORDERING INFORMATION 1 1 1 1 1 1 Y1 Y2 Y3 Y4 Y5 Device MC74VHCT50AD MC74VHCT50ADT MC74VHCT50AM Package SOIC TSSOP SOIC EIAJ Shipping 55 Units/Rail 96 Units/Rail 50 Units/Rail A4 A5 9 11 8 10 FUNCTION TABLE Y6 A Input L H Y Output L H (c) Semiconductor Components Industries, LLC, 2001 1 July, 2001- Rev. 3 Publication Order Number: MC74VHCT50A/D MC74VHCT50A MAXIMUM RATINGS Symbol VCC VIN VOUT IIK IOK IO ICC IGND TSTG TL TJ qJA DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature under Bias Thermal Resistance SOIC TSSOP PD Power Dissipation in Still Air SOIC TSSOP VESD ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Above VCC and Below GND at 85_C (Note 5) 500 450 > 2000 > 200 2000 $300 V 125 170 mW Output in HIGH or LOW State (Note 1) Parameter Value *0.5 to )7.0 *0.5 v VI v )7.0 *0.5 v VO v )7.0 *20 $20 $25 $50 $50 *65 to )150 260 )150 Unit V V V mA mA mA mA mA _C _C _C _C/W ILatch-Up Latch-Up Performance mA Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum-rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22-A114-A. 3. Tested to EIA/JESD22-A115-A. 4. Tested to JESD22-C101-A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Characteristics DC Supply Voltage DC Input Voltage DC Output Voltage VCC = 0 High or Low State Symbol VCC VIN VOUT TA tr , tf Min 4.5 0.0 0.0 0.0 -55 0 0 Max 5.5 5.5 5.5 VCC +125 100 20 Unit V V V C ns/V Operating Temperature Range Input Rise and Fall Time VCC = 3.3 V 0.3 V VCC = 5.0 V 0.5 V http://onsemi.com 2 MC74VHCT50A DC ELECTRICAL CHARACTERISTICS VCC Symbol VIH VIL VOH Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Ou u o age VIN = VIH or VIL VIN = VIH or VIL IOH = -50 A VIN = VIH or VIL IOH = -8 mA VIN = VIH or VIL IOL = 50 A VIN = VIH or VIL IOL = 8 mA VIN = 5.5 V or GND VIN = VCC or GND Input: VIN = 3.4 V VOUT = 5.5 V Test Conditions (V) 4.5 5.5 4.5 5.5 4.5 4.5 4.5 4.5 0 to 5.5 5.5 5.5 0.0 4.4 3.94 0.0 0.1 0.36 0.1 2.0 1.35 0.5 4.5 Min 2.0 2.0 0.8 0.8 4.4 3.80 0.1 0.44 1.0 20 1.50 5.0 TA = 25C Typ Max TA 85C Min 2.0 2.0 0.8 0.8 4.4 3.66 0.1 0.52 1.0 40 1.65 10 Max TA 125C Min 2.0 2.0 0.8 0.8 Max Unit V V V V V V A A mA A VOL Maximum Low-Level Output Voltage Ou u o age VIN = VIH or VIL Maximum Input Leakage Current Maximum Quiescent Supply Current Quiescent Supply Current Output Leakage Current IIN ICC ICCT IOFF II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I I I II I I I I I I I IIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I II I I I I I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I I I I TA = 25C Typ 4.7 5.5 5 TA 85C TA 125C Symbol Parameter Test Conditions Min Max 6.7 7.7 10 Min Max 7.5 8.5 10 Min Max 8.5 9.5 10 Unit ns tPLH, tPHL CIN Maximum Propogation Delay, Input A to Y Maximum Input Capacitance VCC = 5.0 0.5 V CL = 15 pF CL = 50 pF pF Typical @ 25C, VCC = 5.0 V 15 CPD Power Dissipation Capacitance (Note 6) pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. AC ELECTRICAL CHARACTERISTICS (Cload = 50 pF, Input tr = tf = 3.0ns) NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V) TA = 25C Symbol VOLP VOLV VIHD VILD Characteristic Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Typ 0.8 -0.8 Max 1.0 -1.0 2.0 0.8 Unit V V V V http://onsemi.com 3 MC74VHCT50A TEST POINT 3.0V A 50% tPLH 50% VCC tPHL VOH VOL *Includes all probe and jig capacitance GND DEVICE UNDER TEST OUTPUT CL* Y Figure 1. Switching Waveforms Figure 2. Test Circuit MARKING DIAGRAMS (Top View) 14 13 12 11 10 9 8 14 13 12 11 10 9 8 VHCT50A AWLYWW* 1 2 3 4 5 6 7 1 2 3 VHCT 50A ALYW* 4 5 6 7 14-LEAD SOIC D SUFFIX CASE 751A 14 13 12 11 10 9 8 14-LEAD TSSOP DT SUFFIX CASE 948G VHCT50A ALYW* 1 2 3 4 5 6 7 14-LEAD SOIC EIAJ M SUFFIX CASE 965 *See Applications Note #AND8004/D for date code and traceability information. http://onsemi.com 4 MC74VHCT50A PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F -A- 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -B- 1 7 P 7 PL 0.25 (0.010) M B M G C R X 45 _ F -T- SEATING PLANE D 14 PL 0.25 (0.010) M K TB S M A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 http://onsemi.com 5 MC74VHCT50A PACKAGE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B -U- N F DETAIL E K K1 J J1 0.15 (0.006) T U S A -V- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E http://onsemi.com 6 CCC EE CCC EE SECTION N-N -W- MC74VHCT50A PACKAGE DIMENSIONS M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 965-01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --1.42 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.056 14 8 LE Q1 E HE M_ L DETAIL P 1 7 Z D e A VIEW P c b 0.13 (0.005) M A1 0.10 (0.004) http://onsemi.com 7 MC74VHCT50A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC74VHCT50A/D |
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